1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of forming epitaxial layers containing SiGeSn alloys.
2. Description of the Prior Art
In order to increase the carrier mobility of semiconductor structure, it has been widely used to apply tensile stress or compressive stress to a gate channel. For instance, if a compressive stress were to be applied, it has been common in the conventional art to use selective epitaxial growth (SEG) technique to form epitaxial structure such as silicon germanium (SiGe) epitaxial layer in a silicon substrate. As the lattice constant of the SiGe epitaxial layer is greater than the lattice constant of the silicon substrate thereby producing stress to the channel region of PMOS transistor, the carrier mobility is increased in the channel region and speed of MOS transistor is improved accordingly. Conversely, silicon carbide (SiC) epitaxial layer could be formed in silicon substrate to produce tensile stress for gate channel of NMOS transistor.
Despite the aforementioned approach improves the carrier mobility in the channel region, strain of the device cannot be increased significantly as the size of the device decreases to lower electrical resistance in the source/drain region and reach desirable driving current. Hence, how to improve the current fabrication flow has become an important task in this field.